1. Field of the Invention
The present invention relates generally to polycarbosilane generated compositions and methods of manufacture thereof, and more specifically to polyorganosilicon compositions that form low dielectric constant, low moisture absorbing and high glass transition temperature dielectric films or coatings for micro-electronic devices, and methods of manufacture thereof. Additionally, the present invention relates to a method of forming a polycarbosilane derivative as an electrically insulating layer, i.e., a dielectric layer, between metal or other electrically conducting paths or layers in semiconductor devices. The polycarbosilane dielectric layer is referred hereinafter to as an interlayer or interline dielectric layer. Also, the dielectric layer can act as a protective layer for protecting the device from the environment, if it is applied to the top surface of the semiconductor device.
The term "semiconductor device" used herein is intended to mean a variety of devices having a substrate consisting of semiconductor material, such as silicon, having patterned thereon semiconductor integrated circuits (ICs), large scale integration circuits (LSIs), very large scale integration circuits (VLSIs) ultra large scale integration circuits (ULSIs) and the like as well as any other electronic devices employing semiconductor material.
2. Background of the Related Art
In the prior art production of semiconductor integrated circuit devices, fine patterns of semiconductor regions, electrodes, wiring and other components are fabricated onto the semiconductor substrate by using conventional process steps, one being chemical vapor deposition (CVD). After formation of the wire pattern on the device, an interline dielectric material deposition is formed between the horizontally disposed wiring, the pattern overlaid with dielectric film forming material, and multi-layer formation processes, well-known in the art, are provided to form a multi-layered integrated semiconductor device.
Presently, advances in the semiconductor industry are characterized by the introduction of new generations of integrated circuits (ICs) having higher performance and greater functionality than that of previous generations for the purpose of obtaining rapid processing of voluminous information. These advances are often the result of reducing the size of the IC devices; that is, the advances in the integration do not rely upon the expansion of the size or dimension of the device, i.e., the chip, but can be obtained by miniaturizing and increasing the number of components fabricated in the chip and accordingly reducing the dimensions of the chips themselves. As a result, the minimum size of line and space of the wiring in the chips is on the order of submicrons and as a necessity, the wiring structure adopted in current chips is a multi-layer or multi-level wiring or metallization structure.
However, as device geometries in semiconductor wafers approach and then go beyond dimensions as small as 0.25 microns (.mu.m), the dielectric constant of insulating material used between conductive paths, for example silicon oxide (SiO.sub.2), becomes an increasingly significant factor in device performance. As the distance between adjacent conductive paths become smaller, the resulting capacitance, a function of the dielectric property of the insulating material divided by the distance between conductive paths, increases. This causes increased capacitive coupling, or cross-talk, between adjacent conductive paths which carry signals across the chip. The increased capacitance further results in increased power consumption for the IC and an increased RC time constant, the latter resulting in reduced signal propagation speed. In sum, the effects of miniaturization cause increased power consumption, limit achievable signal speed, and degrade noise margins used to insure proper IC device or chip operation.
One way to diminish power consumption and cross talk effects is to decrease the dielectric constant of the insulator, or dielectric, which separates the conductors. Probably the most common semiconductor dielectric is silicon dioxide, which has a dielectric constant (k) of about 3.9. In contrast, air (including partial vacuum) has a dielectric constant of just over 1. Still other insulating materials can provide films having low dielectric constants in the range of approximately 2.0 to 3.0, significantly lower than that of the silicon dioxide films. Therefore, it is well-known that reduced capacitance in the use of certain organic or inorganic insulating materials can result in the alleviation of the aforementioned problems of capacitive coupling and the like. However, any material contemplated for use in semiconductor devices must meet other criteria in addition to a low dielectric constant before it can be used to replace the commonly employed silicon dioxide. For example, any coating material contemplated for use as a dielectric in a semiconductor device should demonstrate the following qualities or characteristics:
1. Excellent Electrical Insulating Properties; PA1 2. High Thermal Stability; PA1 3. Crack Resistance; and PA1 4. Good Adhesion to Underlying Coated Substrates. PA1 R.sub.1, R.sub.7, and R.sub.10 each independently represents a substituted or unsubstituted alkylene, cycloalkylene, or arylene group; PA1 R.sub.2, R.sub.3, R.sub.4, R.sub.5, R.sub.8 and R.sub.9 each independently represents a hydrogen atom or organic group. PA1 R6 represents an organosilicon, a silanyl, a siloxyl, or an organo group; and PA1 x, y, z and w satisfying the conditions of [10&lt;x+y+z+w &lt;100,000], and y and z and w can collectively or independently be zero.
Many dielectric materials have been proposed for use as dielectric film coatings in semi-conductor devices, but most of them are considered to be unsatisfactory in meeting the above-mentioned stringent electrical and physical requirements. The dielectric film forming materials include inorganic materials which are applied over a patterned wiring layered structure by chemical vapor deposition (CVD) processes. Typical examples of useful inorganic dielectric materials include the already cited silicon dioxide (SiO.sub.2), silicon nitride (Si.sub.3 N.sub.4) and phosphosilicate glass (PSG). The preferred formation of these inorganic dielectrics by chemical vapor deposition processes leaves these inorganic dielectric layers inherently uneven because plasma based deposition processes exactly reproduce the uneven and stepped profile structure of the underlying wiring pattern. On the other hand, useful organic/inorganic dielectric materials such as polyimide resins, organic SOG (Spin-On-Glass), and other organic/inorganic dielectric materials have generally been unsatisfactory in one or more of the desired electrical or physical properties of an interlayer dielectric coating outlined above. For example, polyimide resins demonstrate high moisture absorption due to their polarizing chemical structures, which moisture causes an undesirable increase in the dielectric constant of the particular polyimide material being used.
In response to the need for low dielectric coating materials which can be used as a replacement for silicon dioxide, it has been found that certain polycarbosilanes can be subjected to controlled thermal processing to avoid ceramification (oxidation to SiO.sub.2) and form organo-silicon polymers having excellent dielectric properties (low k or low capacitance dielectrics), readily useful as film forming materials in the manufacturer of semiconductor devices. The polyorganosilicon dielectric insulating film materials of the present invention are characterized by a dielectric constant of as low as 2.5, well below that of silicon dioxide, and a capability of formation of globally planarized, thermally stable, and adherent dielectric layers on semiconductor devices, all heretofore unappreciated in the prior art. For example, in U.S. Pat. No. 5,602,060 to Kobayashi there is disclosed a process for preparing semiconductor wafers by applying an organic solvent solution of a particular polycarbosilane onto a wire patterned semiconductor wafer and curing the resulting film layer of the polycarbosilane at temperatures equal to or greater than 350.degree. C. in an oxidizing atmosphere to convert (ceramify) the entire film into a silicon oxide layer. While this patented process has certain advantages in achieving a totally planarized film surface from an organic polycarbosilane precursor, the ultimate silicon dioxide insulating material has an inadequate dielectric constant to meet the new geometries and wiring architecture described above.
In U.S. Pat. No. 5,789,325, to Chandra et al., a polycarbosilane material is dissolved in an organic solvent, spin coated onto an electronically patterned device, and the resulting coating heated in an oxidizing environment for a time sufficient (up to six hours) at high temperatures to ceramify and thereby form a silicon dioxide containing hardened coating on the electronic device. The very purpose of the Chandra et al is the heating of the polycarbosilane coating in an oxidizing environment to attain complete conversion (ceramification) to a to a silica containing coating. The Chandra et al. process is, like that of Kobayashi, inadequate in achieving k values below 3 because the nature of the ultimately formed silicon base coating would inherently have a dielectric constant approximating that of silicon dioxide (3.9).
It has been discovered that certain polycarbosilanes can be subjected to energy generating controlled processes under controlled conditions to generate certain organo silicon films having low dielectric constants and sufficient glass transition temperature values (Tg) above 350.degree. C. so as to form heat resistant semiconductor film coatings, which can withstand the hostile environments of semiconductor plasma processing. The polyorganosilicon coating generating processes can employ any energy source such as thermal (heat) or high energy source such as thermal (heat), electron-beam (e-beam), U.V. light, and any other functional high energy source. These energy sources are applied to the polycarbosilanes of the present invention in a controlled manner to convert the polycarbosilanes to polyorganosilicon materials, which unexpectedly form low k dielectric coatings or films. A preferred high energy processing is the application of thermal (heat) energy to the instant polycarbosilanes in discreet incremental steps of increasing temperature to form the instant low k polyorganosilicon coatings.
These low k polyorganosilicon dielectric coatings of the present invention have good adhesion to a variety of common semiconductor surfaces without the use of adhesive agents. Moreover, the instant polyorganosilicon dielectric coatings possess significant gap filling characteristics, thereby providing complete fill between conductive spaces of 0.25 microns (.mu.m) or less. These low k polyorganosilicon dielectrics also possess sufficient thermal stability so as not to evidence any outgassing during ongoing semiconductor processing, low moisture absorption to retain film resistivity, and stability to a variety of common etching processes. As in the case of applying an organic photoresist film coating to a semiconductor wafer, the present low k polycarbosilane generated dielectric coatings can be easily applied in high yield to electronic substrates using standard spin-bake-cure processing techniques, thereby insuring the cost effectiveness of the polycarbosilane precursor materials. Finally, the polycarbosilane generated dielectric coatings developed and disclosed herein are applicable for use in other micro electronic devices in addition to ICs, for example, printed circuit boards (PCBs), multi-chip modules (MCMs) and the like.